Ver

Version: 0.9.9
Entered-date: 1998-05-13
Description: Structural Verilog compiler for UN*X operating systems. A stand alone simulator (vsim) is included for testing of logic designs. A cycle simulation compiler (cyco) is included which compiles netlists into fast C code. This version includes much richer expression parsing than previous versions. The event simulator has also been speeded up greatly and handles 0, 1, x, z logic levels.
ftp://sunsite.unc.edu/pub/Linux/apps/circuits
ftp://sunsite.unc.edu/pub/Linux/apps/circuits/ver-0.9.9.tgz (195798)
Keywords: Verilog structural HDL digital logic simulator testing cycle simulation
Author: bybell@xxedgexx.com (Tony Bybell)
Maintained-by: bybell@xxedgexx.com (Tony Bybell)
Copying-policy: Freely Distributable

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